1. Field of the Invention
This invention relates to a power circuit and a clock signal detection circuit, and especially relates to those which are applicable to a semiconductor memory device.
2. Description of the Related Art
With the recent remarkable advancement in the micro-miniaturization technique of the semiconductor memory device provided with an extremely large memory capacity, a new problem has come out that the dielectric strength or the withstand voltage of the memory device is more weakened or lowered. In order to manage this problem, the semiconductor memory device such as a synchronous DRAM it (SDRAM) which synchronously operates with the clock signal, is provided with a power circuit which serves to reduce an externally supplied voltage such as 3.3 V to a voltage 2.7 V for use in the memory device.
In the operation of the memory device, as is known, there is a situation in which after receiving the input of an active command, SDRAM is kept in a waiting position i.e. in an active standby mode, for a certain period of time until the next command such as data read or write command is inputted thereto. In order to save the power consumption in such a situation, some measures have been taken so far, for instance interrupting the supply of the clock signal to SDRAM, or invalidating the clock signal by the clock enable signal to stop all the circuits operable with the clock signal.
The power consumption by SDRAM is also increased while SDRAM is in operation for reading/writing data, and this causes the internal voltage to be varied. In order to manage this internal voltage variance, the prior art power circuit which is built in SDRAM is constituted to monitor the internal voltage variance and to immediately compensate it, if any, so as to maintain the constant and stable power supply to the circuit connected with SDRAM.
However, in order that the built-in power circuit may quickly respond to the internal voltage variance, it is needed that the built-in power circuit is additionally provided with another circuit such as an amplifier circuit for amplifying the output power thereof, thereby increasing the internal current in the circuits constituting the power circuit. Consequently, this results in increase in the internal current totally spent by the whole built-in power circuit including the added amplifier circuit. Thus, this raises the power consumption by the entire SDRAM, which is against the purpose of saving the power after all.
Furthermore, while SDRAM stays in the active standby mode, it does not carry out any operation for reading/writing data. In spite of this, the prior art built-in power circuit has to keep the internal current at an increased level, because the built-in power circuit has to quickly respond at any time to the possible internal voltage variance which might be caused by the coming operation of reading/writing data. Consequently, SDRAM has to unnecessarily waste the power whenever it is in the active standby mode.